In the conventional technology, multi-phase signal layout causes delays because of the length of the signal line. Although wafer processing has not entered the sub-micron level, great attention should be paid to layout arrangement in order to avoid serious resistance/capacitance effect, and particularly to avoid excessively long traces which may cause excessive system delay.
In the conventional trace arrangement, the layout proceeds without violating the design rules conventionally implemented at a fabrication facility. However, in the actual circuit layout, the traces exhibit coupling capacitance in between, resulting in undesired effects more serious than expected. Serious interference may occur if the traces of the analog circuit are arranged near the digital circuit. This is especially the case for an analog circuit, which is generally sensitive to trace arrangement or layout.
In addition to the effect caused by coupling capacitance, multi-phase delay time also causes other problems. FIG. 1A is a schematic view showing a layout of multi-phase signal traces in the prior art (Φ0, Φ1, Φ2, and Φ3 denote signals of first, second, third, and fourth phases). Although the signal traces are of equal length, the loading viewed from one signal trace (such as coupling capacitance), may not be identical to that from another signal trace, so that the delay time from the input to the output (td0, td1, td2, and td3), for the signal on each signal trace may vary (td0≠td1≠ . . . ). The varied delay time between phases may influence, for example, the characteristics and performance of a circuit. Therefore, another layout method for multi-phase signal trace has been proposed in the prior art, as shown in FIG. 1B; wherein a grounding trace or a grounding potential GND is provided between each two signal traces in the tracing arrangement. The signal of each phase (Φ0, Φ1, Φ2, and Φ3 ) thus has an equal delay time (td0, td1, td2, and td3) from input to output. However, the layout method in FIG. 1B has other defects. For example, a larger layout area is needed.
The difficulty of how to solve the effect caused by coupling capacitance in the layout method thus becomes an urgent problem requiring solution.